semiconductor

Chiplet：TSMC SoIC-mH Apple M5 Pro_MacBook Pro Cross section and Plane view Analysis Report

M5 Pro PKG Top view
After removing the heatsink

Overview

The SoIC‑mH (Molding‑Horizontal) technology that TSMC is newly introducing into mass production is an advanced chiplet integration method that enables high‑density lateral connections between the CPU and GPU dies, and it is gaining attention as a foundational packaging technology for leading‑edge nodes from 2025 onward.
Cross‑sectional analysis confirms that the CPU and GPU dies are integrated by molding material, and that the Si interposer formed above them plays a central role in die‑to‑die interconnection.
In this analysis, cross‑sectional observations were used to evaluate the die‑to‑die connection scheme (bump structure and pitch) as well as the multilayer structure and thickness of the Si interposer, revealing that the interconnect does not rely on conventional solder‑based bonding. Furthermore, planar analysis confirmed that the ball density reaches approximately eight times that of similar structures from other competitors.

Product Features

Next‑generation processor “Apple M5 Pro
- TSMC’s latest N3P‑generation process
- Implements high‑density lateral connections between the CPU and GPU dies using SoIC‑mH

Report contents

⒈ Cross‑Section Analysis Report (27 pages)
- Connection scheme between the CPU/GPU dies and the Si interposer (bump structure and pitch)
- Connection scheme between the CPU/GPU dies and the memory (bump structure and pitch)
- Layer structure, thickness, and condition of the insulating layers in the Si interposer

⒉ Planar Analysis Report (26 pages)
- Photographs of each layer of the 11‑layer package substrate
- Measurement of minimum feature sizes
- Three‑layer Si interposer: die‑to‑die connection region
- Measurement of minimum feature sizes
- Comparison of bump pitch sizes (vs. Intel Lunar Lake)